NCT7491RQR2G【PDF 48/80 页】IC REMOTE THERMAL MONITOR 24QSOP

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NCT7491

http://onsemi.com

Table 40. REGISTER 0x13 Configuration Register 8 (PowerOn Default = 0xFF)

Bit

Mnemonic

R/W

Description

<0>

Local

R/W

Setting this bit to 1 includes Local temperature in the analog monitoring cycle

<1>

Rem1

R/W

Setting this bit to 1 includes Rem1 temperature in the analog monitoring cycle

<2>

Rem2

R/W

Setting this bit to 1 includes Rem2 temperature in the analog monitoring cycle

<3>

12V

R/W

Setting this bit to 1 includes 12V in the analog monitoring cycle

<4>

R/W

Setting this bit to 1 includes 5V in the analog monitoring cycle

<5>

Vccp

R/W

Setting this bit to 1 includes Vccp in the analog monitoring cycle

<6>

2.5V

R/W

Setting this bit to 1 includes 2.5V in the analog monitoring cycle

<7>

Vcc

R/W

Setting this bit to 1 includes Vcc in the analog monitoring cycle errors.

Table 41. PWM STEPPING LEVEL REGISTERS (PowerOn Default = 0x00)

R/W

Description

0x14

PWMStep1

R/W

Sets the PWM level on a THERM assertion if THERM stepping is enabled

0x15

PWMStep2

R/W

Sets the PWM level if THERM stepping is enabled and the temperature is greater

than THERM + Step (Note 6)

6. The temperature interval for each step is programmed in registers 0x18 and 0x19

Table 42. REGISTER 0x16 THERM Configuration Register 1 (PowerOn Default = 0x1C)

Bit

Mnemonic

R/W

Description

<1:0>

TMRP

R/W

00 = Disabled

01 = Pin 14 (QSOP), Pin 11 (QFN) is THERM timer input

10 = Pin 19 (QSOP), Pin 16 (QFN) is THERM timer input

11 = Pin 22 (QSOP), Pin 19 (QFN) is THERM timer input

<2>

Max/Full 1

R/W

1= PWM1 goes to 100% on THERM

0= PWM1 goes to Max programmed PWM on THERM

<3>

Max/Full 2

R/W

1= PWM2 goes to 100% on THERM

0= PWM2 goes to Max programmed PWM on THERM

<4>

Max/Full 3

R/W

1= PWM3 goes to 100% on THERM

0= PWM3 goes to Max programmed PWM on THERM

<5>

Push

THERM

R/W

1 = THERM assertions enabled for Push temperatures

0 = THERM assertions disabled for Push temperatures

<6>

SMBus

THERM

R/W

1 = THERM assertions enabled for SMBus slave temperatures

0 = THERM assertions disabled for SMBus slave temperatures

<7>

Reserved

Table 43. REGISTER 0x17 THERM Configuration Register 2 (PowerOn Default = 0x07)

Bit

Mnemonic

R/W

Description

<0>

P1TH

R/W

If set to 1 then PWM1 will respond to THERM events

<1>

P2TH

R/W

If set to 1 then PWM2 will respond to THERM events

<2>

P3TH

R/W

If set to 1 then PWM3 will respond to THERM events

<3>

Reserved

<4>

Reserved

<5>

Reserved

<6>

Reserved

<7>

Reserved

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